Schematic review
Someone with no stake in the design and no memory of how it was done last time reads every net, before it goes to layout or to fab.
The things competence doesn’t protect you from
Assume the engineer who drew this is good and short of time, because that is usually true. The defects that survive to a schematic review are rarely ignorance. They are the integration seams between blocks that came from different places, the assumption nobody wrote down, the vendor reference design adopted without checking whether its application conditions match yours, and the part that got onto the BOM by inertia.
So that is where I look hardest. Where the style changes between one sheet and the next, the thinking usually stopped. Where two sub-circuits meet and neither author owned the join, something is usually wrong with the join.
The rest is method: every rail traced to every load, every sequencing requirement checked against the actual datasheet clause, every non-obvious component value checked against what it is supposed to set.
The first question I will ask you
Which sub-circuits are reused, copied or adapted, and from where. Previous project, vendor reference design, app note, evaluation board.
That one question surfaces more integration defects than any other, and almost nobody volunteers the answer.
What gets worked through
Power architecture
Rail by rail load budget with margin. Topology choice and whether it is defensible. Regulator selection against the actual load, not the datasheet’s example. Feedback networks, current limits, soft start, inrush, hold-up. Bulk and decoupling against the real impedance target rather than a capacitor per pin.
Sequencing, reset and supervision
Every device’s sequencing requirement checked against the datasheet clause, not against habit. Power-good chains, supervisor thresholds against worst-case tolerance, brown-out behaviour, and what the board does on a power-down that isn’t clean.
Clocking and distribution
Source selection, accuracy and stability against what the interfaces need. Distribution topology and termination. Loading, drive strength and jitter budget. What happens on clock loss, and whether anything notices.
Digital interfaces
DDR, high-speed serial, LVDS, source-synchronous, and the quiet ones: I2C addressing and bus loading, SPI mode agreement, UART levels, and whether the JTAG chain is actually usable for bring-up.
Analog and mixed signal
Front-end error budget where one exists, and a flag where one doesn’t. Reference selection and drift. ADC and DAC drive, anti-alias filtering, and the grounding assumptions the schematic is quietly making.
Protection and interfaces
ESD, surge, reverse polarity, hot-plug, overvoltage. Fault current paths, and whether they run through anything not designed to carry them. Isolation barriers and everything that quietly bypasses them.
Parts, derating and supply
Voltage, current, power and temperature derating against a stated policy. Capacitor DC bias derating, which is where a surprising number of designs quietly lose most of their capacitance. Lifecycle status, lead time and second source.
Test, documentation and rationale
Bring-up provisions, test points, debug access, and whether a new engineer could bring this board up from what is on the page. Whether design rationale is captured anywhere, because a design nobody can defend is one nobody can safely change.
What a finding looks like
Every finding states what I saw, why it matters, and the evidence, with the datasheet section cited. Where the fix is obvious I point at it in a line and stop there.
The example alongside is representative in shape rather than a real client’s board. The “why it matters” paragraph is the part that does the work: it is what tells you whether I understood your design or pattern-matched against a checklist.
SCH-001 · S1 BLOCKER · PWR · CONFIDENCE HIGH
VDDIO enable violates the device sequencing requirement
Observation. VDD and VDDIO on U12 share a single enable net and rise together, within roughly 200 µs of each other.
Why it matters. With VDDIO present before VDD has established, the IO ring can latch into a state that draws well above the specified inrush. On a single power-up it may survive. Across thermal cycling and repeated power cycles it degrades, and the failure presents as an intermittent that is very hard to attribute back to sequencing.
Evidence. Device datasheet rev 3.2, §7.3.1, p.41: VDD must reach 90% of its final value before VDDIO is enabled.
Direction. Sequence VDDIO from a supervisor or from the VDD power-good output. A discrete supervisor is more defensible than an RC delay, which drifts with temperature and load.
The package
- Schematic, all sheets, as a searchable PDF. Native CAD project as well if you can share it, because pin types and connectivity can then be inspected rather than inferred.
- BOM with manufacturer part numbers, tolerance, voltage rating, dielectric and package.
- Block diagram and power tree, even hand drawn.
- Datasheets for the main devices, or just the part numbers and I will source them.
- Operating environment: temperature range, vibration, humidity, altitude, expected life.
- Applicable standards and any certification target.
- Which blocks are reused, copied or adapted, and from where.
- Anything you are already worried about.
Everything at one consistent revision, please. The full list comes with the proposal.
Depth
| Tier | Depth | From |
|---|---|---|
| Scan 3 days | Structural read-through. Power tree sanity, obvious sequencing and protection gaps, package reviewability. No independent recalculation. | £750 +VAT |
| Standard 7 days | Full checklist. Rail-by-rail load budget, interface-by-interface pass, BOM cross-check, spot recalculation of dividers, current limits and pull-ups. | £2,750 +VAT |
| Deep 15 days | Adds independent recalculation of every value that sets a threshold or time constant, worst-case tolerance analysis, line-by-line derating audit, sneak-path search, obsolescence audit, and reading the CAD database rather than the plot. | £6,500 +VAT |
Starting prices. Where a job lands within a tier depends on size and complexity, and the proposal carries one firm number before anything begins.
Reviewing something else?
Four review types, run to the same standard. Two in one engagement takes 10% off the second.
Have a schematic you’d like read properly?
Thirty minute scoping call, no charge. Tell me the sheet count and what’s worrying you and I will tell you which tier fits.